FIG. 1 shows an embodiment of a computing system. The exemplary computing system of FIG. 1 includes: 1) one or more processors 101; 2) a cache 102; 3) a memory controller (or memory control hub (MCH)) 103; 4) a system memory 104 (of which different types exist such as DDR, RDRAM, SDRAM, EDO RAM, etc,); 5) a graphics processor 106; 6) a display/screen 106 (of which different types exist such as Cathode Ray Tube (CRT), TFT, LCD, etc.); and, 7) an I/O control hub (ICH) 107.
The one or more processors 101 execute instructions in order to perform whatever software routines the computing system implements. The instructions frequently involve some sort of operation performed upon data. Both data and instructions are stored in system memory 104 and cache 102. Cache 102 is typically designed to have shorter latency times than system memory 104. For example, cache 102 might be integrated onto the same silicon chip(s) as the processor(s) and/or constructed with faster SRAM cells whilst system memory 104 might be constructed with slower DRAM cells.
By tending to store more frequently used instructions and data in the cache 102 as opposed to the system memory 104, the overall performance efficiency of the computing system improves. System memory 104 is deliberately made available to other components within the computing system. For example, the data received from various interfaces to the computing system (e.g., keyboard and mouse, printer port, LAN port, modem port, etc.) or retrieved from an internal storage element of the computing system (e.g., hard disk drive) are often temporarily queued into system memory 104 prior to their being operated upon by the one or more processor(s) 101 in the implementation of a software program.
Similarly, data that a software program determines should be sent from the computing system to an outside entity through one of the computing system interfaces, or stored into an internal storage element, is often temporarily queued in system memory 104 prior to its being transmitted or stored. The ICH 107 is responsible for ensuring that such data is properly passed between the system memory 104 and its appropriate corresponding computing system interface (and internal storage device if the computing system is so designed). The memory controller 103 is responsible for managing the various contending requests for system memory 104 access amongst the processor(s) 101, interfaces and internal storage elements that may proximately arise in time with respect to one another.
Another computing system component that the memory controller 103 may have to deal with (because it requests access to the system memory 104) is the graphics processor 105. The graphics processor 105 can be viewed as a co-processor that “takes on” the responsibility of performing sophisticated instructions associated with the presentation of complex visual images on the computing system's display 106. By removing such responsibility from processor(s) 101, the performance efficiency of the processor(s) is improved. The graphics processor 105 is designed to execute display image specific instructions so that display image specific software routines can be executed.
FIG. 2 shows a more detailed depiction of an interface between a memory controller 203 and a memory 204. As observed in FIG. 2, the interface between the memory controller 203 and the memory 204 includes an address bus 201 and a data bus 202. The memory 204 can be viewed as having two basic functions: read and write. During a write cycle information (e.g., data, instructions, etc.) is written into specific locations of memory 204. During a read cycle information is read from specific locations memory 204.
The address bus 201 is driven by the memory controller and can be viewed as the wiring where the specific memory locations mentioned above are identified for both write cycles and read cycles. The data bus 202 is the wiring that transports the information written to memory 204 during a write cycle and read from memory 204 during a read cycle. Note that the data bus is “bi-directional” in that the information written into memory 204 during a write cycle is driven across the data bus 202 by the memory controller 203 to the memory 204; while, by contrast, the information read from memory 204 during a read cycle is driven across the data bus 202 by the memory 204.
Memory 204 typically has an associated “data width” of M bits which corresponds to the amount of information (in bits) that can be written to or read from a specific location (referred to as an “address”) that is identified by the memory controller 203 on address bus 201. As such, the data bus 202 is likewise implemented as a bus of width M.